OpenBTS: E110 Compile UHD dari Release Bukan git

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Compile UHD

Download

opkg remove --force-depends uhd uhd-dev uhd-examples uhd-tests
echo "/usr/local/lib" >> /etc/ld.so.conf
cd ~/src
wget http://files.ettus.com/binaries/uhd_stable/uhd_003.005.003-release/uhd-source_003.005.003-release.tar.gz
tar zxvf uhd-source_003.005.003-release.tar.gz

Compile

mkdir ~/src/uhd-source_003.005.003-release/build
cd ~/src/uhd-source_003.005.003-release/build
cmake -DCMAKE_TOOLCHAIN_FILE=../cmake/Toolchains/arm_cortex_a8_native.cmake -DENABLE_E100=ON -DENABLE_USRP_E_UTILS=TRUE -DENABLE_USRP2=OFF -DENABLE_USRP1=OFF -DENABLE_B100=OFF ../
make
make test
make install
ldconfig

Install Image 003.004.002-180-gb6bb13bc

rm -Rf /usr/share/uhd/images/*
rm -Rf /usr/local/share/uhd/images/*
cd ~
tar zxvf uhd-images_003.004.002-180-gb6bb13bc.tar.gz
mv ~/uhd-images_003.004.002-180-gb6bb13bc/share/uhd/images/* /usr/local/share/uhd/images/


Download UHD Images

Alternatif lain yang lebih baik adalah download UHD Image. Download Image UHD 003.005.003 

sudo /usr/local/lib/uhd/utils/uhd_images_downloader.py

Images successfully installed to: /usr/local/share/uhd/images

Perbaiki PATH

PATH=$PATH:/usr/local/bin
export PATH

Test

Test clock 52MHz 

cd /usr/local/bin
./uhd_usrp_probe --args="master_clock_rate=52e6"

Hasilnya 

linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.003-175-g09de3c07

-- Opening device node /dev/usrp_e0...
-- Initializing FPGA clock to 52.000000MHz...
-- USRP-E100 clock control: 12
--   r_counter: 2
--   a_counter: 4
--   b_counter: 19
--   prescaler: 8
--   vco_divider: 2
--   chan_divider: 15
--   vco_rate: 1560.000000MHz
--   chan_rate: 780.000000MHz
--   out_rate: 52.000000MHz
-- 
.. dst

Test Benchmark 

cd ~/src/uhd.git/host/build/examples
./benchmark_rate --rx_rate 1000000 --tx_rate 1000000

Hasilnya kira-kira 

linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.003-175-g09de3c07

Creating the usrp device with: ...
-- Opening device node /dev/usrp_e0...
-- Initializing FPGA clock to 64.000000MHz...
-- USRP-E100 clock control: 10
--   r_counter: 2
--   a_counter: 0
--   b_counter: 20
--   prescaler: 8
--   vco_divider: 5
--   chan_divider: 5
--   vco_rate: 1600.000000MHz
--   chan_rate: 320.000000MHz
--   out_rate: 64.000000MHz
-- 
-- Performing wishbone readback test... pass
Using Device: Single USRP:
  Device: E-Series Device
  Mboard 0: E110
  RX Channel: 0
    RX DSP: 0
    RX Dboard: A
    RX Subdev: RFX1800 RX
  TX Channel: 0
    TX DSP: 0
    TX Dboard: A
    TX Subdev: RFX1800 TX

Testing receive rate 1.000000 Msps
Testing transmit rate 1.000000 Msps

Benchmark rate summary:
  Num received samples:    9996012
  Num dropped samples:     0
  Num overflows detected:  0
  Num transmitted samples: 10254075
  Num sequence errors:     0
  Num underflows detected: 0

Done!

Pranala Menarik

Persiapan

OpenBTS 2.6

OpenBTS 2.8

Multi OpenBTS 2.8

Ettus E110

GPRS

Power Amplifier

Lain Lain

Catatan Legal dan Pendukung

Catatan Sejarah

Dokumentasi Video

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