OpenBTS: E110 Cek Daughter Board

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LED di Muka

LED di muka akan berguna untuk melakukan debugging hardware dan software. 

LED A: transmitting
LED B: fpga loaded
LED C: receiving
LED D: fpga loaded
LED E: reference lock
LED F: board power

Ubah Master Clock ke 52MHz

Untuk keperluan OpenBTS kita perlu mengubah master clock ke 52MHz. Hal ini dapat dilakukan menggunakan perintah 

uhd_usrp_probe --args="master_clock_rate=52e6"

Ini tidak permanen rupanya

Cek Menggunakan uhd_find_devices

ketik 

uhd_find_devices

Hasilnya 

linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db

--------------------------------------------------
-- UHD Device 0
--------------------------------------------------
Device Address:
    type: e100
    node: /dev/usrp_e0
    name: 
    serial: EBR10Z9E2

Cek Menggunakan uhd_usrp_probe

Tulis 

uhd_usrp_probe
uhd_usrp_probe --args="model=E110"

Hasilnya 

linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db

-- Opening device node /dev/usrp_e0...
-- Initializing FPGA clock to 64.000000MHz...
-- USRP-E100 clock control: 10
--   r_counter: 2
--   a_counter: 0
--   b_counter: 20
--   prescaler: 8
--   vco_divider: 5
--   chan_divider: 5
--   vco_rate: 1600.000000MHz
--   chan_rate: 320.000000MHz
--   out_rate: 64.000000MHz
-- 
-- Performing wishbone readback test... pass
  _____________________________________________________
 /
|       Device: E-Series Device
|     _____________________________________________________
|    /
|   |       Mboard: E110 (euewanee)
|   |   vendor: 3
|   |   device: 1
|   |   revision: 4
|   |   content: 0
|   |   model: E110
|   |   serial: EBR10Z9E2
|   |   
|   |   Time sources: none, external, _external_
|   |   Clock sources: internal, external, auto
|   |   Sensors: ref_locked
|   |     _____________________________________________________
|   |    /
|   |   |       RX DSP: 0
|   |   |   Freq range: -32.000 to 32.000 Mhz
|   |     _____________________________________________________
|   |    /
|   |   |       RX DSP: 1
|   |   |   Freq range: -32.000 to 32.000 Mhz
|   |     _____________________________________________________
|   |    /
|   |   |       RX Dboard: A
|   |   |   ID: RFX1800 (0x0034)
|   |   |   Serial: E1R11X8R8
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Subdev: 0
|   |   |   |   Name: RFX RX
|   |   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   |   Sensors: lo_locked, rssi
|   |   |   |   Freq range: 1500.000 to 2100.000 Mhz
|   |   |   |   Gain range PGA0: 0.0 to 70.0 step 0.0 dB
|   |   |   |   Connection Type: QI
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Codec: A
|   |   |   |   Name: ad9522
|   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB
|   |     _____________________________________________________
|   |    /
|   |   |       TX DSP: 0
|   |   |   Freq range: -32.000 to 32.000 Mhz
|   |     _____________________________________________________
|   |    /
|   |   |       TX Dboard: A
|   |   |   ID: RFX1800 (0x0035)
|   |   |   Serial: E1R11X8R8
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Subdev: 0
|   |   |   |   Name: RFX TX
|   |   |   |   Antennas: TX/RX, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 1500.000 to 2100.000 Mhz
|   |   |   |   Gain Elements: None
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: Yes
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Codec: A
|   |   |   |   Name: ad9522
|   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB


Compatibility Error

Kalau keluar Error 

-- Performing wishbone readback test... pass
Error: RuntimeError: Expected FPGA compatibility number 9, but got 8:
The FPGA build is not compatible with the host code build.

SOLUSI:

Lakukan Instalasi UHD Image Tepatnya, download dari 

http://files.ettus.com/uhd_releases/master_images/

tar zxvf UHD-images-003.004.000-f500b92.tar.gz 
cd UHD-images-003.004.000-f500b92/share/uhd/images/
cp * /usr/share/uhd/images/

Cek Menggunakan lantency_test

Tulis perintah 

root@usrp-e1xx:/usr/share/uhd/examples# latency_test

Hasilnya 

linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db

-- Opening device node /dev/usrp_e0...
-- Initializing FPGA clock to 64.000000MHz...
-- USRP-E100 clock control: 10
--   r_counter: 2
--   a_counter: 0
--   b_counter: 20
--   prescaler: 8
--   vco_divider: 5
--   chan_divider: 5
--   vco_rate: 1600.000000MHz
--   chan_rate: 320.000000MHz
--   out_rate: 64.000000MHz
-- 
-- Performing wishbone readback test... pass

UHD Warning:
    The hardware does not support the requested TX sample rate:
    Target sample rate: 25.000000 MSps
    Actual sample rate: 21.333333 MSps
Actual TX Rate: 21.333333 Msps...

UHD Warning:
    The hardware does not support the requested RX sample rate:
    Target sample rate: 25.000000 MSps
    Actual sample rate: 21.333333 MSps
Actual RX Rate: 21.333333 Msps...

ACK 999, UNDERFLOW 0, TIME_ERR 1, other 0


Cek Menggunakan USRP E Utils

Menggunakan usrp-e-loopback 

/usr/share/uhd/usrp_e_utils/usrp-e-loopback 

setup memory mapped ring buffer... done
start write thread... 
start read thread... 
..........
seq_errors          0
checksum_errors     0
sent_words32        47972576
recvd_words32       47745124
approx send rate    4.79726Msps
approx recv rate    4.77451Msps


Menggunakan usrp-e-wb-test 

/usr/share/uhd/usrp_e_utils/usrp-e-wb-test 

num pass: 0     num fail: 0
num pass: 1000000       num fail: 0
num pass: 2000000       num fail: 0
num pass: 3000000       num fail: 0
num pass: 4000000       num fail: 0
num pass: 5000000       num fail: 0
num pass: 6000000       num fail: 0
num pass: 7000000       num fail: 0
num pass: 8000000       num fail: 0
num pass: 9000000       num fail: 0
num pass: 10000000
num fail: 0


Cek usrp_siggen.py

uhd_siggen.py -f 1700000000
uhd_siggen.py -f 1800000000
uhd_siggen.py -f  900000000

Referensi

Pranala Menarik

Persiapan

OpenBTS 2.6

OpenBTS 2.8

Ettus E110

Lain Lain

Catatan Legal dan Pendukung

Catatan Sejarah

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