Difference between revisions of "OpenBTS: E110 Cek Daughter Board"

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(New page: ==Cek Menggunakan uhd_usrp_probe == uhd_usrp_probe linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db -- Opening device node /dev/usrp_e0... ...)
 
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==Cek Menggunakan  uhd_usrp_probe ==
 
==Cek Menggunakan  uhd_usrp_probe ==
 +
 +
Tulis
  
 
  uhd_usrp_probe
 
  uhd_usrp_probe
 +
 +
Hasilnya
  
 
  linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db
 
  linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db
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  |  |  |  |      TX Codec: A
 
  |  |  |  |      TX Codec: A
 
  |  |  |  |  Name: ad9522
 
  |  |  |  |  Name: ad9522
  |  |  |  |  Gain range pga: -20.0 to 0.0 step 0.1 dB  
+
  |  |  |  |  Gain range pga: -20.0 to 0.0 step 0.1 dB
 
 
 
 
  
 
==Cek Menggunakan lantency_test==
 
==Cek Menggunakan lantency_test==

Revision as of 07:14, 23 February 2012

Cek Menggunakan uhd_usrp_probe

Tulis

uhd_usrp_probe

Hasilnya

linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db

-- Opening device node /dev/usrp_e0...
-- Initializing FPGA clock to 64.000000MHz...
-- USRP-E100 clock control: 10
--   r_counter: 2
--   a_counter: 0
--   b_counter: 20
--   prescaler: 8
--   vco_divider: 5
--   chan_divider: 5
--   vco_rate: 1600.000000MHz
--   chan_rate: 320.000000MHz
--   out_rate: 64.000000MHz
-- 
-- Performing wishbone readback test... pass
  _____________________________________________________
 /
|       Device: E-Series Device
|     _____________________________________________________
|    /
|   |       Mboard: E110 (euewanee)
|   |   vendor: 3
|   |   device: 1
|   |   revision: 4
|   |   content: 0
|   |   model: E110
|   |   serial: EBR10Z9E2
|   |   
|   |   Time sources: none, external, _external_
|   |   Clock sources: internal, external, auto
|   |   Sensors: ref_locked
|   |     _____________________________________________________
|   |    /
|   |   |       RX DSP: 0
|   |   |   Freq range: -32.000 to 32.000 Mhz
|   |     _____________________________________________________
|   |    /
|   |   |       RX DSP: 1
|   |   |   Freq range: -32.000 to 32.000 Mhz
|   |     _____________________________________________________
|   |    /
|   |   |       RX Dboard: A
|   |   |   ID: RFX1800 (0x0034)
|   |   |   Serial: E1R11X8R8
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Subdev: 0
|   |   |   |   Name: RFX RX
|   |   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   |   Sensors: lo_locked, rssi
|   |   |   |   Freq range: 1500.000 to 2100.000 Mhz
|   |   |   |   Gain range PGA0: 0.0 to 70.0 step 0.0 dB
|   |   |   |   Connection Type: QI
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Codec: A
|   |   |   |   Name: ad9522
|   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB
|   |     _____________________________________________________
|   |    /
|   |   |       TX DSP: 0
|   |   |   Freq range: -32.000 to 32.000 Mhz
|   |     _____________________________________________________
|   |    /
|   |   |       TX Dboard: A
|   |   |   ID: RFX1800 (0x0035)
|   |   |   Serial: E1R11X8R8
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Subdev: 0
|   |   |   |   Name: RFX TX
|   |   |   |   Antennas: TX/RX, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 1500.000 to 2100.000 Mhz
|   |   |   |   Gain Elements: None
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: Yes
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Codec: A
|   |   |   |   Name: ad9522
|   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB

Cek Menggunakan lantency_test

root@usrp-e1xx:/usr/share/uhd/examples# latency_test 
linux; GNU C++ version 4.5.3 20110311 (prerelease); Boost_104500; UHD_003.004.000-7dc76db

-- Opening device node /dev/usrp_e0...
-- Initializing FPGA clock to 64.000000MHz...
-- USRP-E100 clock control: 10
--   r_counter: 2
--   a_counter: 0
--   b_counter: 20
--   prescaler: 8
--   vco_divider: 5
--   chan_divider: 5
--   vco_rate: 1600.000000MHz
--   chan_rate: 320.000000MHz
--   out_rate: 64.000000MHz
-- 
-- Performing wishbone readback test... pass

UHD Warning:
    The hardware does not support the requested TX sample rate:
    Target sample rate: 25.000000 MSps
    Actual sample rate: 21.333333 MSps
Actual TX Rate: 21.333333 Msps...

UHD Warning:
    The hardware does not support the requested RX sample rate:
    Target sample rate: 25.000000 MSps
    Actual sample rate: 21.333333 MSps
Actual RX Rate: 21.333333 Msps...

ACK 999, UNDERFLOW 0, TIME_ERR 1, other 0




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