Intel Nehalem (microarchitecture)

Initial Nehalem processors use the same 45 nm manufacturing methods as Penryn. A working system with two Nehalem processors was shown at Intel Developer Forum Fall 2007, and a large number of Nehalem systems were shown at Computex in June 2008.

The microarchitecture is named after the Nehalem Native American nation in Oregon. At that stage it was supposed to be the latest evolution of the NetBurst microarchitecture. Since the abandonment of NetBurst, the codename has been recycled and refers to a completely different project, although Nehalem still has some things in common with NetBurst. Nehalem-based microprocessors utilize higher clock speeds and are more energy-efficient than Penryn microprocessors. Hyper-Threading is reintroduced along with an L3 Cache missing from most Core-based microprocessors.

The first computer to use Nehalem-based Xeon processors was the Apple Mac Pro workstation announced on March 3, 2009. Nehalem-based Xeon EX processors for larger servers were expected in Q4 2009 based on initial announcements from Intel, but in November 2009 the launch of these processors was pushed back to the first half of 2010.

Mobile Nehalem-based processors were introduced in September 2009.

Technology

Microarchitecture of the quad-core implementation

Various sources have stated the specifications of processors in the Nehalem family:

• Two or four
  • 731 million transistors for the quad core variant
• 45 nm manufacturing process
• Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM channels
• Integrated graphics processor (IGP) located off-die, but in the same CPU package
• A new point-to-point processor interconnect, the Intel QuickPath Interconnect, in high-end models, replacing the legacy front side bus
• Integration of PCI Express and Direct Media Interface into the processor in mid-range models, replacing the northbridge
• Simultaneous multithreading (SMT) by multiple cores which enables two threads per core. Intel calls this hyper-threading. Simultaneous multithreading has not been present on a consumer desktop Intel processor since 2006 with the Pentium 4 and Pentium XE. Intel reintroduced SMT with their Atom Architecture.
• Native (monolithic, i.e. all processor cores on a single die) quad- and octal-core processors
• The following caches:
  • 32 KB L1 instruction and 32 KB L1 data cache per core
  • 256 KB L2 cache per core
  • 4–8 MB L3 cache shared by all cores
• 33% more in-flight micro-ops than Conroe
• Second-level branch predictor and second-level translation lookaside buffer
• Modular blocks of components such as cores that can be added and subtracted for varying market segments

Performance and power improvements

It has been reported that Nehalem will have a focus on performance, which accounts for the increased core size. Compared to Penryn, Nehalem will have:

• 1.1x to 1.25x the single-threaded performance or 1.2x to 2x the multithreaded performance at the same power level
• 30% lower power usage for the same performance
• According to a preview from AnandTech "expect a 20–30% overall advantage over Penryn with a 10% increase in power usage."
• Per Core, clock-for-clock, Nehalem will provide a 15–20% increase in performance compared to Penryn.

PC Watch found that a Nehalem "Gainestown" processor has 1.6x the SPECint_rate2006 integer performance and 2.4x the SPECfp_rate_2006 floating-point performance of a 3.0 GHz Xeon X5365 "Clovertown" quad-core processor.

A 2.93 GHz Nehalem "Bloomfield" system has been used to run a 3DMark Vantage benchmark and gave a CPU score of 17,966. The 2.66 GHz variant scores 16,294. A 2.4 GHz Core 2 Duo E6600 scores 4,300.

AnandTech tested the Intel QuickPath Interconnect ("QPI", 4.8 GT/s version) and found the copy bandwidth using triple-channel 1066 MHz DDR3 was 12.0 GB/s. A 3.0 GHz Core 2 Quad system using dual-channel 1066 MHz DDR3 achieved 6.9 GB/s.

Overclocking will be possible with Bloomfield processors and the X58 chipset. The Lynnfield processor will use a PCH removing the need for a northbridge chipset.

The Nehalem processors are the first to incorporate the SSE 4.2 SIMD instructions, adding 7 new instructions to the SSE 4.1 set available in the Core 2 series.

Code names

Each combination of a Nehalem/Westmere processor die and package has both a separate codename and a product code. Typically, the same dies are used for uniprocessor (UP) and dual-processor (DP) servers, but using an extra QuickPath link for the inter-processor communication in the DP server variant. Where the Core microarchitecture used four different processor sockets, one for each market segment, Nehalem now uses Socket 1366 for the high-end of both UP and DP machines, and Socket 1156 for the low end UP machines. The name for the UP version of Gulftown is not yet known; its product code is 80613 and can be found in Intel's product database

	Mobile	Desktop UP Server	DP Server	MP Server
Dual-Core 45 nm Dual-Channel, PCIe, Graphics Core	Auburndale canceled	Havendale canceled
Dual-Core 32 nm Dual-Channel, PCIe, Graphics Core	Arrandale 80617	Clarkdale 80616
Quad-Core 45 nm Dual-Channel, PCIe	Clarksfield 80607	Lynnfield 80605	Jasper Forest 80612
Quad-Core 45 nm Triple-Channel		Bloomfield 80601	Gainestown 80602
Six-Core 32 nm Triple-Channel		Gulftown 80613	Gulftown 80614
Eight-Core 45 nm Triple-Channel				Beckton 80604

Variants

These tables list all the processors of Nehalem microarchitecture to have been leaked so far. The table is ordered roughly by performance, which usually correlates with price and power. Released processors are set in bold.

Notes:

• "Extreme" processors have an unlocked clock multiplier. Thermal design power (TDP) values for CPUs with integrated GPUs include the GPU.
• All variants have 64 KiB L1 cache per core, and 256 KiB L2 cache per core.

45 nm processors

Codename	Market	Cores (Threads)	Socket	Brand	Processor No.	Clock rate			Turbo	TDP	Interfaces			L3 cache	Release	1k Unit Price