Difference between revisions of "List of Intel Core 2 microprocessors"

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(New page: The '''Core 2''' brand refers to Intel's x86/x86-64 microprocessors (with the eighth-generation microarchitecture, named Core architecture) targeted at the cons...)
 
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The '''[[Core 2]]''' brand refers to [[Intel]]'s [[x86]]/[[x86-64]] [[microprocessor]]s (with the eighth-generation [[microarchitecture]], named [[Core architecture]]) targeted at the consumer and business markets (except the servers) above [[Pentium Dual-Core]].  The [[Core 2]] '''Duo''' branch covered [[dual-core]] [[CPU]]s for both desktop and notebook computers, '''Core 2 Quad''' - [[quad-core]] CPUs for both desktop and notebook computers, and '''Core 2 Extreme''' - dual-core and quad-core CPUs for both desktop and notebook computers.
 
  
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==Desktop processors==
 
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===Dual-Core Desktop processors===
 
−
====Core 2 Duo====
 
−
=====[[Conroe (microprocessor)#Allendale|"Allendale"]] (65 nm)=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management)''
 
−
* [[Die (integrated circuit)|Die]] size: 111 mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|L2]]{{ref label|MoreAgressiveHaltState|3|a}}, [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|M0]]{{ref label|MoreAgressiveHaltState|4|b}}, [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|G0]]
 
−
{{cpulist|core|head}} <!-- edit Template:cpulist to modify the style of this table -->
 
−
{{cpulist|core|conroe|model=Core 2 Duo E4300|sspec1=SL9TB|sspec2=SLA99|step1=L2|step2=M0|mult= 9|l2=2|fsb=800|vmin=0.850|vmax=1.500|date=January 21, 2007|part1=HH80557PG0332M|price=$163|links=1}}
 
−
{{cpulist|core|conroe|model=Core 2 Duo E4400|sspec1=SLA3F|sspec2=SLA98|step1=L2|step2=M0|mult=10|l2=2|fsb=800|vmin=0.962|vmax=1.325|date=April 22, 2007  |part1=HH80557PG0412M|price=$133}}
 
−
{{cpulist|core|conroe|model=Core 2 Duo E4500|sspec1=SLA95            |step1=M0        |mult=11|l2=2|fsb=800|vmin=0.962|vmax=1.325|date=July 22, 2007  |part1=HH80557PG0492M|price=$133}}
 
−
{{cpulist|core|conroe|model=Core 2 Duo E4600|sspec1=SLA94            |step1=M0        |mult=12|l2=2|fsb=800|vmin=1.162|vmax=1.312|date=October 21, 2007|part1=HH80557PG0562M|price=$133}}
 
−
{{cpulist|core|conroe|model=Core 2 Duo E4700|sspec1=SLALT            |step1=G0        |mult=13|l2=2|fsb=800|vmin=1.162|vmax=1.312|date=March 2, 2008  |part1=HH80557PG0642M|price=$133}}
 
−
{{end}}
 
−
 
−
{{note label|MoreAgressiveHaltState|3|a}}
 
−
Note: The [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|L2 Stepping]] as well as the models with sSpec SL9ZL, SL9ZF, SLA4U, SLA4T have better optimizations to lower the idle power consumption from 22W to 12W.
 
−
 
−
Note: The [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|M0 and G0 Steppings]] have better optimizations to lower idle power consumption from 12W to 8W.
 
−
 
−
See also: Versions of the same Allendale core with half the L2 cache disabled are available under the [[List of Intel Pentium Dual-Core microprocessors#"Allendale" (65 nm)|Pentium Dual-Core]] brand.
 
−
 
−
=====[[Conroe (microprocessor)|"Conroe"]] (65 nm)=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]]'' {{ref label|NoTXT|a|a}}
 
−
* [[Die (integrated circuit)|Die]] size: 111&nbsp;mm² (Allendale), 143&nbsp;mm² (Conroe)
 
−
* [[Stepping (version numbers)|Steppings]]:[[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|B2, G0]] (Conroe), [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|L2]] (Allendale)
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|conroe|model=Core 2 Duo E6300|sspec1=SL9SA|step1=B2|freq=1866|l2=2|fsb=1066|mult=7|vmin=0.85|vmax=1.3525|date=July 27, 2006|part1=HH80557PH0362M|price=$183|links=1}}
 
−
|Core 2 Duo E6320 || SLA4U (B2) || 1866 MHz || 4 MB || 1066 MT/s || 7x || 0.85 - 1.325 V || 65 W || LGA 775 || April 22, 2007 || HH80557PH0364M || $163
 
−
|-
 
−
|Core 2 Duo E6300 || SL9TA (L2) || 1866 MHz || 2 MB || 1066 MT/s || 7x || 1.225 - 1.325 V || 65 W || LGA 775 || January 2007 || HH80557PH0362M || $183
 
−
|-
 
−
|Core 2 Duo E6400 || SL9S9 (B2) || 2133 MHz || 2 MB || 1066 MT/s || 8x || 0.85 - 1.3525 V || 65 W || LGA 775 || July 27, 2006 || HH80557PH0462M || $224
 
−
|-
 
−
|Core 2 Duo E6400 || SL9T9 (L2) || 2133 MHz || 2 MB || 1066 MT/s || 8x || 1.225 - 1.325 V || 65 W || LGA 775 || January 2007 || HH80557PH0462M || $224
 
−
|-
 
−
|Core 2 Duo E6420 || SLA4T (B2) || 2133 MHz || 4 MB || 1066 MT/s || 8x || 1.187 - 1.325 V || 65 W || LGA 775 || April 22, 2007 || HH80557PH0464M || $183
 
−
|-
 
−
|Core 2 Duo E6540{{ref label|NoTXT|a|a}}|| SLAA5 (G0) || 2333 MHz || 4 MB || 1333 MT/s || 7x || 0.962 - 1.350 V || 65 W || LGA 775 || July 22, 2007 || HH80557PJ0534M || $163
 
−
|-
 
−
|Core 2 Duo E6550 || SLA9X (G0) || 2333 MHz || 4 MB || 1333 MT/s || 7x  || 0.962 - 1.350 V || 65 W || LGA 775 || July 22, 2007 || HH80557PJ0534MG || $163
 
−
|-
 
−
|Core 2 Duo E6600 || SL9S8, SL9ZL (B2){{ref label|MoreAgressiveHaltState|3|a}} || 2400 MHz || 4 MB || 1066 MT/s || 9x  || 0.85 - 1.325 V || 65 W || LGA 775 || July 27, 2006 || HH80557PH0564M || $316
 
−
|-
 
−
|Core 2 Duo E6700 || SL9S7, SL9ZF (B2){{ref label|MoreAgressiveHaltState|3|a}} || 2667 MHz || 4 MB || 1066 MT/s || 10x || 0.85 - 1.325 V || 65 W || LGA 775 || July 27, 2006 || HH80557PH0674M || $530
 
−
|-
 
−
|Core 2 Duo E6750 || SLA9V (G0) || 2667 MHz || 4 MB || 1333 MT/s || 8x || 0.962 - 1.350 V || 65 W || LGA 775 || July 22, 2007 || HH80557PJ0674MG || $183
 
−
|-
 
−
|Core 2 Duo E6850 || SLA9U (G0) || 3000 MHz || 4 MB || 1333 MT/s || 9x || 0.962 - 1.350 V || 65 W || LGA 775 || July 22, 2007 || HH80557PJ0804MG || $266
 
−
{{end}}
 
−
 
−
{{note label|NoTXT|a|a}}Note: The E6540 does not support Intel's [[Trusted Execution Technology|TXT]].
 
−
 
−
=====[[Conroe (microprocessor)|"Conroe-CL"]] (65 nm)=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]]''
 
−
* [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² (Conroe)
 
−
* [[Stepping (version numbers)|Steppings]]: ?
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|conroe|model=Core 2 Duo E6305|sspec1=SLAGF|freq=1866|l2=2|fsb=1066|mult=7|sock=[[LGA 771]]|part1=HH80557KH036F|links=1}}
 
−
{{cpulist|core|conroe|model=Core 2 Duo E6405|sspec1=SLAGG|freq=2133|l2=4|fsb=1066|mult=8|sock=[[LGA 771]]|part1=HH80557KH046F}}
 
−
{{end}}
 
−
 
−
===== [[Wolfdale (microprocessor)#Wolfdale-3M|"Wolfdale-3M"]] (45 nm) =====
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management)
 
−
* [[Die (integrated circuit)|Die]] size: 82&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|M0, R0]]
 
−
* Models with a part number ending in "ML" support [[Intel VT]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|wolfdale|model=Core 2 Duo E7200 |l2=3 |fsb=1066 |mult=9.5  |vmin=0.85 |vmax=1.3625 |date=April 20, 2008,
 
−
  |price=$113 |sspec1=SLAPC |step1=M0 |part1=EU80571PH0613M |sspec2=SLAVN |step2=M0}}
 
−
{{cpulist|core|wolfdale|model=Core 2 Duo E7300 |l2=3 |fsb=1066 |mult=10  |vmin=0.85 |vmax=1.3625 |date=August 10, 2008
 
−
  |price=$113 |sspec1=SLAPB |step1=M0 |part1=EU80571PH0673M
 
−
              |sspec2=SLB9X |step2=R0 |part2=AT80571PH0673M
 
−
              |sspec3=SLGA9 |step3=R0 <!-- also AT80571PH0673M, no VT version --> }}
 
−
{{cpulist|core|wolfdale|model=Core 2 Duo E7400 |l2=3 |fsb=1066 |mult=10.5 |vmin=0.85 |vmax=1.3625 |date=October 19, 2008
 
−
  |price=$133 |sspec1=SLB9Y |step1=R0 |part1=AT80571PH0723M
 
−
              |sspec2=SLGQ8 |step2=R0 <!-- also AT80571PH0723M -->
 
−
              |sspec3=SLGW3 |step3=R0, with VT |part2=AT80571PH0723ML  }}
 
−
{{cpulist|core|wolfdale|model=Core 2 Duo E7500 |l2=3 |fsb=1066 |mult=11  |vmin=0.85 |vmax=1.3625 |date=January 18, 2009
 
−
  |price=$113 |sspec1=SLB9Z |step1=R0 |part1=AT80571PH0773M
 
−
              |sspec2=SLGTE |step2=R0, with VT |part2=AT80571PH0773ML}}
 
−
{{cpulist|core|wolfdale|model=Core 2 Duo E7600 |l2=3 |fsb=1066 |mult=11.5 |vmin=0.85 |vmax=1.3625 |date=May 31, 2009
 
−
  |price=$133 |sspec1=SLGTD |step1=R0, with VT |part1=AT80571PH0833ML}}
 
−
{{end}}
 
−
 
−
===== [[Wolfdale (microprocessor)#Wolfdale|"Wolfdale"]] (45 nm)=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 ([[Intel Active Management Technology]]), [[Intel VT]] {{ref label|NoTXT|a|a}}, [[Trusted Execution Technology|TXT]] {{ref label|NoTXT|b|b}}''
 
−
* [[Die (integrated circuit)|Die]] size: 107&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0, E0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|wolfdale|model=Core 2 Duo E8190 {{ref label|NoTXT|a|c}} {{ref label|NoTXT|b|b}}|sspec1=SLAQR|step1=C0|freq=2667|l2=6|fsb=1333|mult=8|vmin=0.85|vmax=1.3625|date=January 20, 2008|part1=EU80570PJ0676MN|price=$163|links=1}}
 
−
|Core 2 Duo E8200 || SLAPP (C0) || 2667 MHz || 6 MB || 1333 MT/s || 8x || 0.85 – 1.3625 V || 65 W || LGA 775 || January 20, 2008 || EU80570PJ0676M || $163
 
−
|-
 
−
|Core 2 Duo E8300 || SLAPJ (C0)<br>SLAPN (C0) || 2833 MHz || 6 MB || 1333 MT/s || 8.5x || 0.85 – 1.3625 V || 65 W || LGA 775 || April 20, 2008 || EU80570AJ0736M<br>EU80570PJ0736M || $163
 
−
|-
 
−
|rowspan=2| Core 2 Duo E8400 || SLAPL (C0) || rowspan=2| 3000 MHz || rowspan=2| 6 MB || rowspan=2| 1333 MT/s || rowspan=2| 9x || rowspan=2| 0.85 – 1.3625 V || rowspan=2| 65 W || rowspan=2| LGA 775 || January 20, 2008 || EU80570PJ0806M || $183
 
−
|-
 
−
|SLB9J (E0) || July 18, 2008 || AT80570PJ0806M || $183
 
−
|-
 
−
|rowspan=2| Core 2 Duo E8500 || SLAPK (C0) || rowspan=2| 3166 MHz || rowspan=2| 6 MB || rowspan=2 | 1333 MT/s || rowspan=2| 9.5x || rowspan=2| 0.85 – 1.3625 V || rowspan=2| 65 W || rowspan=2|LGA 775 || January 20, 2008 || EU80570PJ0876M  || $266
 
−
|-
 
−
|SLB9K (E0) || || AT80570PJ0876M ||
 
−
|-
 
−
| Core 2 Duo E8600 || SLB9L (E0) || 3333 MHz || 6 MB || 1333 MT/s || 10x || 0.85 - 1.3625 V || 65 W || LGA 775 || August 10, 2008 || AT80570PJ0936M || $266
 
−
{{end}}
 
−
 
−
{{note label|NoTXT|a|a}}Note: E8190 does not support Intel Virtualization Technology.
 
−
 
−
See also: Versions of the same Wolfdale core in an LGA 771 are available under the [[List of Intel Xeon microprocessors#"Wolfdale-DP" (standard-voltage, 45 nm)|Dual-Core Xeon]] brand.
 
−
 
−
====Core 2 Extreme====
 
−
=====[[Conroe (microprocessor)#Conroe XE|"Conroe XE"]] (65 nm)=====
 
−
 
−
''These models features an [[CPU locking|unlocked]] [[clock multiplier]]''
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]]''
 
−
* [[Die (integrated circuit)|Die]] size: 143&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|B1, B2]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|conroe|model=Core 2 Extreme X6800|sspec1=SL9S5|step1=B2|freq=2933|l2=4|fsb=1066|mult=11|vmin=0.85|vmax=1.5|tdp=75|date=July 27, 2006|part1=HH80557PH0677M|part2=BX80557X6800|price=$999|links=1}} 
 
−
{{end}}
 
−
 
−
===Quad-Core Desktop processors===
 
−
====Core 2 Quad====
 
−
=====[[Kentsfield (microprocessor)|"Kentsfield"]] (65 nm)=====
 
−
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]]
 
−
* [[Die (integrated circuit)|Die]] size: 2 &times;143&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|B3, G0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|kentsfield|model=Core 2 Quad Q6400|sspec1=SL9UN|step1=B3|freq=2133|l2=8|fsb=1066|mult=8|tdp=105|vmin=1.1|vmax=1.372|part1=HH80562PH0468M|price=OEM|links=1}}
 
−
{{cpulist|core|kentsfield|model=Core 2 Quad Q6600|sspec1=SL9UM|step1=B3|l2=8|fsb=1066|mult=9|tdp=105|vmin=1.1|vmax=1.372|date=January 7, 2007|part1=HH80562PH0568M|part2=BX80562Q6600|price=$851}}
 
−
{{cpulist|core|kentsfield|model=Core 2 Quad Q6600|sspec1=SLACR|step1=G0|l2=8|fsb=1066|mult=9 |tdp=95|vmin=1.1|vmax=1.372|date=April 20, 2007|part1=HH80562PH0568M|part2=BX80562Q6600|part3=BXC80562Q6600|price=$266}}
 
−
{{cpulist|core|kentsfield|model=Core 2 Quad Q6700|sspec1=SLACQ|step1=G0|l2=8|fsb=1066|mult=10|tdp=95|vmin=1.1|vmax=1.372|date=April 20, 2007|part1=HH80562PH0678M|part2=BX80562Q6700|part3=BXC80562Q6700|price=$530}}
 
−
{{end}}
 
−
 
−
===== [[Yorkfield (microprocessor)#Yorkfield-6M|"Yorkfield-6M"]] (45 nm) =====
 
−
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management)''
 
−
* [[Die (integrated circuit)|Die]] size: 2 × 82&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|M0, M1, R0]]
 
−
* All Q9x00 models support: [[Intel VT]], [[Trusted Execution Technology|TXT]]''
 
−
* All Q9x05 models support: Intel VT
 
−
* All Q8xxx models are Yorkfield-6M MCMs with only 2 x 2 MB L2 cache enabled.
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q8200 |l2=4|fsb=1333|mult=7  |vmin=0.85|vmax=1.3625|      date=August 31, 2008  |price=$224
 
−
      |sspec1=SLB5M|step1=M1|sspec2=SLG9S|step2=R0|part1=EU80580PJ0534MN|part2=AT80580PJ0534MN}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q8200S|l2=4|fsb=1333|mult=7  |vmin=0.85|vmax=1.3625|tdp=65|date=January 18, 2009 |price=$245
 
−
      |part1=AT80580AJ0534MN|part2=AT80580AJ0534ML|sspec1=SLG9T|step1=R0|sspec2=SLGSS|step2=R0, with Intel VT}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q8300 |l2=4|fsb=1333|mult=7.5|vmin=0.85|vmax=1.3625|tdp=95|date=November 30, 2008|price=$224
 
−
      |part1=AT80580PJ0604MN|sspec2=SLGUR|step2=R0, with Intel VT)|part2=AT80580PJ0604ML|sspec1=SLB5W|step1=R0}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q8400 |l2=4|fsb=1333|mult=8  |vmin=0.85|vmax=1.3625|tdp=95|date=April 19, 2009  |price=$183
 
−
      |part1=AT80580PJ0674ML|sspec1=SLGT6|step1=R0, with Intel VT}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q8400S|l2=4|fsb=1333|mult=8  |vmin=0.85|vmax=1.3625|tdp=65|date=April 19, 2009  |price=$245
 
−
      |part1=AT80580AJ0674ML|sspec1=SLGT7|step1=R0, with Intel VT}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q9300 |l2=6|fsb=1333|mult=7.5|vmin=0.85|vmax=1.3625|tdp=95|date=March 10, 2008  |price=$266
 
−
      |part1=EU80580PJ0606M |sspec1=SLAMX|step1=M0|sspec2=SLAWE|step2=M1}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q9400 |l2=6|fsb=1333|mult=8  |vmin=0.85|vmax=1.3625|tdp=95|date=August 10 2008  |price=$266
 
−
      |part1=AT80580PJ0676M |sspec1=SLB6B|step1=R0}}               
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q9400S|l2=6|fsb=1333|mult=8  |vmin=0.85|vmax=1.3625|tdp=65|date=January 18 2009  |price=$320
 
−
      |part1=AT80580AJ0676M |sspec1=SLG9U|step1=R0}}   
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q9500|l2=6|fsb=1333|mult=8.5|vmin=0.85|vmax=1.3625|date=January 17, 2010|price=$183}}         
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q9505 |l2=6|fsb=1333|mult=8.5|vmin=0.85|vmax=1.3625|tdp=95|date=August 31, 2009  |price=$213
 
−
      |part1=AT80580PJ0736MG|sspec1=SLGYY|step1=R0}}               
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q9505S|l2=6|fsb=1333|mult=8.5|vmin=0.85|vmax=1.3625|tdp=65|date=August 31, 2009  |price=$277   
 
−
      |part1=AT80580AJ0736MG|sspec1=SLGYZ|step1=R0}}             
 
−
{{end}}
 
−
 
−
===== [[Yorkfield (microprocessor)|"Yorkfield"]] (45 nm) =====
 
−
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]]''
 
−
* [[Die (integrated circuit)|Die]] size: 2 × 107&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0, C1, E0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Quad Q9450|sspec1=SLAN6|step1=C0|sspec2=SLAWR|step2=C1|freq=2667|l2=12|fsb=1333|mult=8|vmin=0.85|vmax=1.3625|tdp=95|date=March 25, 2008|part1=EU80569PJ067N|price=$316|links=1}}
 
−
|rowspan=2| Core 2 Quad Q9550 || SLAWQ (C1) ||rowspan=2| 2833 MHz ||rowspan=2| 2 × 6 MB ||rowspan=2| 1333 MT/s ||rowspan=2| 8.5x ||rowspan=2| 0.85 – 1.3625 V ||rowspan=2| 95 W ||rowspan=2| LGA 775 || March 2008 || EU80569PJ073N || $530
 
−
|-
 
−
|SLB8V (E0) || August 2008 || AT80569PJ073N || $316
 
−
|-
 
−
| Core 2 Quad Q9550S || SLGAE (E0) || 2833 MHz || 2 × 6 MB || 1333 MT/s || 8.5x || 0.85 – 1.3625 V || 65 W || LGA 775 || January 18, 2009 || AT80569AJ073N || $369
 
−
|-
 
−
| Core 2 Quad Q9650 || SLB8W (E0) || 3000 MHz || 2 × 6 MB || 1333 MT/s || 9x || 0.85 – 1.3625 V || 95 W || LGA 775 || August 10, 2008 || AT80569PJ080N || $530
 
−
{{end}}
 
−
 
−
====Core 2 Extreme====
 
−
=====[[Kentsfield (microprocessor)#Kentsfield XE|"Kentsfield XE"]] (65 nm)=====
 
−
 
−
''These models feature an [[CPU locking|unlocked]] [[clock multiplier]]''
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]]''
 
−
* [[Die (integrated circuit)|Die]] size: 2 &times;143&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|B3, G0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|kentsfield|model=Core 2 Extreme QX6700|sspec1=SL9UL|step1=B3|freq=2667|l2=8|fsb=1066|mult=10|vmin=1.1|vmax=1.372|tdp=130||date=November 14, 2006|part1=HH80562PH0678M|price=$999|links=1}}
 
−
|rowspan=2|Core 2 Extreme QX6800 || SL9UK (B3) ||rowspan=2| 2933 MHz ||rowspan=2| 2 &times; 4 MB ||rowspan=2| 1066 MT/s ||rowspan=2| 11x ||rowspan=2| 1.1 - 1.372 V ||rowspan=2| 130 W ||rowspan=2| LGA 775 || April 9, 2007 || HH80562PH0778M || $1199
 
−
|-
 
−
|SLACP (G0) || July 16, 2007 || HH80562XH0778M || $999
 
−
|-
 
−
{{cpulist|core|kentsfield|model=Core 2 Extreme QX6850|sspec1=SLAFN|step1=G0|freq=3000|l2=8|fsb=1333|mult=9|vmin=1.1|vmax=1.372|tdp=130||date=July 16, 2007|part1=HH80562XJ0808M|price=$999}}
 
−
{{end}}
 
−
 
−
=====[[Yorkfield (microprocessor)#Yorkfield XE|"Yorkfield XE"]] (45 nm)=====
 
−
*These models feature an [[CPU locking|unlocked]] [[clock multiplier]]''
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]]''
 
−
* I/O Acceleration Technology (Intel I/OAT) supported by: QX9775
 
−
* [[Die (integrated circuit)|Die]] size: 2 &times; 107&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0, C1]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Extreme QX9650|sspec1=SLAN3|step1=C0|sspec2=SLAWN|step2=C1|freq=3000|l2=12|fsb=1333|mult=9|vmin=0.85|vmax=1.3625|tdp=130|date=November 11, 2007|part1=EU80569XJ080NL|price=$999|links=1}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Extreme QX9770|sspec1=SLAN2|step1=C0|sspec2=SLAWM|step2=C1|freq=3200|l2=12|fsb=1600|mult=8|vmin=0.85|vmax=1.3625|tdp=136|date=March 24, 2008|part1=EU80569XL088NL|price=$1399}}
 
−
{{cpulist|core|yorkfield|model=Core 2 Extreme QX9775|sspec1=SLANY|step1=C0|freq=3200|l2=12|fsb=1600|mult=8|volt=1.212 V|tdp=150|sock=[[LGA 771]]|date=March 24, 2008|part1=EU80574XL088N|price=$1499}}
 
−
{{end}}
 
−
 
−
==Notebook (mobile) processors==
 
−
===Single-Core Notebook processors===
 
−
====Core 2 Solo====
 
−
===== [[Merom (microprocessor)#Merom-L|"Merom-L"]] (ultra-low-voltage, 65 nm)=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]],  [[Trusted Execution Technology|TXT]]''
 
−
* [[Die (integrated circuit)|Die]] size: 81&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|A1]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|merom|model=Core 2 Solo ULV U2100|sspec1=SLAGM|step1=A1|freq=1066|l2=1|fsb=533|mult=8|vmin=0.860|vmax=0.975|tdp=5.5|sock=[[Micro-FCBGA]]|date=September 2, 2007|part1=LE80537UE0041M|price=$241|links=1}}
 
−
{{cpulist|core|merom|model=Core 2 Solo ULV U2200|sspec1=SLAGL|step1=A1|step2=A1|freq=1200|l2=1|fsb=533|mult=9|vmin=0.860|vmax=0.975|tdp=5.5|sock=Micro-FCBGA|date=September 2, 2007|part1=LE80537UE0091M|price=$262}}
 
−
{{end}}
 
−
 
−
===== [[Penryn (microprocessor)#Penryn-L|"Penryn-L"]] (ultra-low-voltage, 45 nm, Small Form Factor)=====
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]], IDA (Intel Dynamic Acceleration)'', No [[Hyper-threading]]
 
−
* [[Socket P]] processors are capable of throttling the FSB anywhere between 400-800 MHz as necessary.
 
−
* [[Die (integrated circuit)|Die]] size: 82&nbsp;mm²
 
−
* 410 million transistors
 
−
* Package size: 22&nbsp;mm × 22&nbsp;mm
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|M0, R0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Solo SU3300|sspec1=SLGAR|step1=M0|sspec2=SLGAJ|step2=R0|mult=6|fsb=800|l2=3|vmin=1.05|vmax=1.15|tdp=5.5|date=May 2008|part1=AV80585UG0093M|price=$262|links=1}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Solo SU3500|sspec1=SLGFM|step1=R0|mult=7|fsb=800|l2=3|vmin=1.02|vmax=1.15|tdp=5.5|date=Q2 2009|part1=AV80585UG0173M|price=$262}}
 
−
{{end}}
 
−
 
−
===Dual-Core Notebook processors===
 
−
====Core 2 Duo====
 
−
=====[[Merom (microprocessor)|"Merom"]], [[Merom (microprocessor)#Merom-2M|"Merom-2M"]] (standard-voltage, 65 nm) {{anchors|"Merom-2M" (standard-voltage, 65 nm)|"Merom" (standard-voltage, 65 nm)}} =====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management)''
 
−
* Model 7600G features an unlocked clock multiplier and can be overclocked up to 3.16 GHz.
 
−
* ''[[Intel VT]]'': Supported by T5500 (those with stepping L2 only), T5600 and all T7xxx
 
−
* ''Intel Dynamic Front Side Bus Frequency Switching'': Supported by [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|E1, G0, G2, M0 Steppings]]
 
−
* Socket P processors are capable of throttling the FSB anywhere between 400-800 MHz as necessary.
 
−
* [[Die (integrated circuit)|Die]] size: 143&nbsp;mm² (Merom), 111&nbsp;mm² (Merom-2M)
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|B2, E1, G0, G2]] (Merom), [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|L2, M0]] (Merom-2M)
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|merom|model=Core 2 Duo T5200|sspec1=SL9VP|step1=B2|freq=1600|l2=2|fsb=533|mult=12|vmin=1.0375|vmax=1.3|tdp=34|sock=[[Socket M]]|date=October 2006|part1=LF80537GE0252M|price= [[Original equipment manufacturer|OEM]]|links=1}}
 
−
|Core 2 Duo T5250 || SLA9S (M0) || 1500 MHz || 2 [[Megabyte|MB]]  || 667 [[Megatransfer|MT/s]] || 9x || 1.0375 - 1.3 V || 35 W || [[Socket P]] || Q2 2007 || LF80537GF0212M || OEM
 
−
|-
 
−
|Core 2 Duo T5270 || SLALK (M0) || 1400 MHz || 2 MB  || 800 MT/s || 7x || 1.0375 - 1.3 V || 35 W || Socket P || October 2007 || LF80537GG0172M || OEM
 
−
|-
 
−
|Core 2 Duo T5300 || SL9WE (L2) || 1733 MHz || 2 MB || 533 MT/s || 13x || 1.0375 - 1.3 V || 34 W || [[Socket M]] || Q1 2007 || LF80537GE0302M || OEM
 
−
|-
 
−
|Core 2 Duo T5450 || SLA4F (M0) || 1667 MHz || 2 MB  || 667 MT/s || 10x || 1.0375 - 1.3 V || 35 W || Socket P || Q2 2007 || LF80537GF0282MT || OEM
 
−
|-
 
−
|Core 2 Duo T5470 || SLAEB (M0) || 1600 MHz || 2 MB  || 800 MT/s || 8x || 1.0375 - 1.3 V || 35 W || Socket P || July 2007 || LF80537GG0252M || OEM
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T5500 || SL9SH (B2)<br>SLGFK (G2) ||rowspan=2 | 1667 MHz ||rowspan=2 | 2 MB ||rowspan=2 | 667 MT/s ||rowspan=2 | 10x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 34 W || Socket M ||rowspan=2 | August 28, 2006 || LF80537GF0282M ||rowspan=2 | $209
 
−
|-
 
−
| SL9SQ (B2) || FCBGA6 || LE80537GF0282M
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T5500 || SL9U4 (L2)<br>SLA4F (M0)||rowspan=2 | 1667 MHz ||rowspan=2 | 2 MB ||rowspan=2 | 667 MT/s ||rowspan=2 | 10x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 34 W || Socket M ||rowspan=2 | Q1 2007 || LF80537GF0282M ||rowspan=2 | $209
 
−
|-
 
−
| SL9U8 (L2) || FCBGA6 || LE80537GF0282M
 
−
|-
 
−
|Core 2 Duo T5550 || SLA4E (M0) || 1833 MHz || 2 MB || 667 MT/s || 11x || 1.075 - 1.175 V || 35 W || Socket P || January 2008 || LF80537GF0342MT || OEM
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T5600 || SL9SG (B2) ||rowspan=2 | 1833 MHz ||rowspan=2 | 2 MB ||rowspan=2 | 667 MT/s ||rowspan=2 | 11x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 34 W || Socket M || rowspan=2 |August 28, 2006 || LF80537GF0342M ||rowspan=2 | $241
 
−
|-
 
−
| SL9SP (B2) || FCBGA6 || LE80537GF0342M
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T5600 || SL9U3 (L2)<br>SLA4E (M0) ||rowspan=2 | 1833 MHz ||rowspan=2 | 2 MB ||rowspan=2 | 667 MT/s ||rowspan=2 | 11x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 34 W || Socket M ||rowspan=2 | Q1 2007 || LF80537GF0342M ||rowspan=2 | $241
 
−
|-
 
−
| SL9U7 (L2) || FCBGA6|| LE80537GF0342M
 
−
|-
 
−
|Core 2 Duo T5670 || SLAJ5 (M0) || 1800 MHz || 2 MB  || 800 MT/s || 9x || 1.0375 - 1.3 V || 35 W || Socket P || Q2 2008 || LF80537GG0332MN || OEM
 
−
|-
 
−
|Core 2 Duo T5750 || SLA4D (M0) || 2000 MHz || 2 MB || 667 MT/s || 12x || 1.0375 - 1.3 V || 35 W || Socket P || January 2008 || LF80537GF0412M || OEM
 
−
|-
 
−
|Core 2 Duo T5800 || SLB6E (M0) || 2000 MHz || 2 MB || 800 MT/s || 10x || 1.0375 - 1.3 V || 35 W || Socket P || March 2008 || LF80537GG041F || OEM
 
−
|-
 
−
|Core 2 Duo T5850 || SLA4C (M0) || 2167 MHz || 2 MB || 667 MT/s || 13x || 1.0375 - 1.3 V || 35 W || Socket P || March 2008 || LF80537GF0482M || OEM
 
−
|-
 
−
|Core 2 Duo T5870 || SLAZR (M0) || 2000 MHz || 2 MB  || 800 MT/s || 10x || 1.0375 - 1.3 V || 35 W || Socket P || 2008 || LF80537GG0412MN || OEM
 
−
|-
 
−
|Core 2 Duo T5900 || SLB6D (M0) || 2200 MHz || 2 MB || 800 MT/s || 11x || 1.0375 - 1.3 V || 35 W || Socket P ||  || LF80537GG049F || OEM
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T7100 || SLA4A (M0) ||rowspan=2 | 1800 MHz ||rowspan=2 | 2 MB ||rowspan=2 | 800 MT/s ||rowspan=2 | 9x ||rowspan=2 | 0.900 - 1.175 V ||rowspan=2 | 35 W || Socket P ||rowspan=2 | May 9, 2007 || LF80537GG0332M ||rowspan=2 | $209
 
−
|-
 
−
| SLA3U (M0) || FCBGA6 || LE80537GG0332M
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T7250 || SLA49 (M0) || rowspan=2 |2000 MHz || rowspan=2 |2 MB || rowspan=2 |800 MT/s || rowspan=2 |10x || rowspan=2 |1.075 - 1.175 V || rowspan=2 |35 W || Socket P || rowspan=2 |September 2, 2007 || LF80537GG0412M || rowspan=2 | $290
 
−
|-
 
−
| SLA3T (M0) || FCBGA6 || LE80537GG0412M
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T7200 || SL9SF (B2) ||rowspan=2 | 2000 MHz ||rowspan=2 | 4 MB ||rowspan=2 | 667 MT/s ||rowspan=2 | 12x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 34 W || Socket M ||rowspan=2 | August 28, 2006 || LF80537GF0414M ||rowspan=2 | $294
 
−
|-
 
−
| SL9SL (B2) || FCBGA6 || LE80537GF0414M
 
−
|-
 
−
|-|rowspan=2 |Core 2 Duo T7250 || SLA3T (M0) ||rowspan=2 | 2000 MHz ||rowspan=2 | 4 MB ||rowspan=2 | 800 MT/s ||rowspan=2 | 10x ||rowspan=2 | 1.075 - 1.175 V ||rowspan=2 | 35 W || [[Socket M]] ||rowspan=2 | [Unknown] || LF80537GG0414M ||rowspan=2
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T7300 || SLA45 (E1) ||rowspan=2 | 2000 MHz ||rowspan=2 | 4 MB ||rowspan=2 | 800 MT/s ||rowspan=2 | 10x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 35 W || [[Socket P]] ||rowspan=2 | May 9, 2007 || LF80537GG0414M ||rowspan=2 | $241
 
−
|-
 
−
| SLA3P (E1) || FCBGA6 || LE80537GG0414M
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T7400 || SL9SE (B2)<br>SLGFJ (G2) ||rowspan=2 | 2166 MHz ||rowspan=2 | 4 MB ||rowspan=2 | 667 MT/s ||rowspan=2 | 13x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 34 W || Socket M ||rowspan=2 | August 28, 2006 || LF80537GF0484M ||rowspan=2 | $423
 
−
|-
 
−
| SL9SK (B2)<BR>SLGFV (G2) || FCBGA6 || LE80537GF0484M
 
−
|-
 
−
|rowspan=4 |Core 2 Duo T7500 || SLA44 (E1) ||rowspan=4 | 2200 MHz ||rowspan=4 | 4 MB ||rowspan=4 | 800 MT/s ||rowspan=4 | 11x ||rowspan=4 | 1.0375 - 1.3 V ||rowspan=4 | 35 W || Socket P ||rowspan=2 | May 9, 2007 || LF80537GG0494M ||rowspan=2 | $316
 
−
|-
 
−
| SLA3N (E1) || FCBGA6 || LE80537GG0494M
 
−
|-
 
−
| SLAF8 (G0) || Socket P ||rowspan=2 |September 2, 2007 || LF80537GG0494M ||rowspan=2 | $241
 
−
|-
 
−
| SLADM (G0) || FCBGA6 || LE80537GG0494M
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T7600 || SL9SD (B2) ||rowspan=2 | 2333 MHz ||rowspan=2 | 4 MB ||rowspan=2 | 667 MT/s ||rowspan=2 | 14x ||rowspan=2 | 1.0375 - 1.3 V ||rowspan=2 | 34 W || Socket M ||rowspan=2 | August 28, 2006 || LF80537GF0534M ||rowspan=2 | $637
 
−
|-
 
−
| SL9SJ (B2) || FCBGA6 || LE80537GF0534M
 
−
|-
 
−
|Core 2 Duo T7600G || SL9SD (B2) || 2333 MHz || 4 MB || 667 MT/s || 14x || N/A || N/A || Socket M || December, 2006 || LF80537GF0534MU || N/A
 
−
|-
 
−
|rowspan=4 |Core 2 Duo T7700 || SLA43 (E1) ||rowspan=4 | 2400 MHz ||rowspan=4 | 4 MB ||rowspan=4 | 800 MT/s ||rowspan=4 | 12x ||rowspan=4 | 1.0375 - 1.3 V ||rowspan=4 | 35 W || Socket P ||rowspan=2 | May 9, 2007 || LF80537GG0564M ||rowspan=2 | $530
 
−
|-
 
−
| SLA3M (E1) || FCBGA6 || LE80537GG0564M
 
−
|-
 
−
| SLAF7 (G0) || Socket P ||rowspan=2 |September 2, 2007 || LF80537GG0564M ||rowspan=2 | $316
 
−
|-
 
−
| SLADL (G0) || FCBGA6 || LE80537GG0564M
 
−
|-
 
−
|rowspan=2 |Core 2 Duo T7800 || SLAF6 (G0) || rowspan=2 |2600 MHz ||rowspan=2 |4 MB ||rowspan=2 |800 MT/s ||rowspan=2 |13x ||rowspan=2 |1.0375 - 1.3 V ||rowspan=2 |35 W || Socket P ||rowspan=2 |September 2, 2007 || LF80537GG0644ML ||rowspan=2 | $530
 
−
|-
 
−
| SLA75 (G0) || FCBGA6 || LE80537GG0644M
 
−
|}
 
−
 
−
See also: Versions of the same Merom-2M core with half the L2 cache disabled are available under the [[List of Intel Pentium Dual-Core microprocessors#.22Merom-2M.22 .2865 nm.29|Pentium Dual-Core]] brand.
 
−
 
−
===== "Merom" (low-voltage, 65 nm)=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]]''
 
−
* ''Intel Dynamic Front Side Bus Frequency Switching'': Supported by [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|E1, G0, G2 Steppings]]
 
−
* [[Die (integrated circuit)|Die]] size: 143&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|B2, E1, G0, G2]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|merom|model=Core 2 Duo SL7100|freq=1200|l2=4|fsb=800|tdp=12|sock=[[µFC-BGA 956]]|price=OEM|links=1
 
−
  |part1=SY80537LG0094M|sspec1=SLAJD|sspec2=SLAT4}}
 
−
{{cpulist|core|merom|model=Core 2 Duo LV L7200 |l2=4|fsb=667|mult=8|vmin=0.9|vmax=1.2|tdp=17|sock=FCBGA6|date=Q1 2007|price=$284
 
−
  |part1=LE80537LF0144M|sspec1=SL9SN|step1=B2}}
 
−
{{cpulist|core|merom|model=Core 2 Duo LV L7300 |l2=4|fsb=800|mult=7|vmin=0.9|vmax=1.1|tdp=17|sock=FCBGA6|date=May 2007|price=$284
 
−
  |part1=LE80537LG0174M|sspec1=SLA3S|step1=E1}}
 
−
{{cpulist|core|merom|model=Core 2 Duo LV L7400 |l2=4|fsb=667|mult=9|vmin=0.9|vmax=1.2|tdp=17|sock=FCBGA6|date=Q1 2007|price=$316
 
−
  |part1=LE80537LF0214M|sspec1=SL9SM|step1=B2|sspec2=SLGFX|step2=G2}}
 
−
{{cpulist|core|merom|model=Core 2 Duo LV L7500 |l2=4|fsb=800|mult=8|vmin=0.9|vmax=1.1|tdp=17|sock=FCBGA6|date=May 2007|price=$316
 
−
  |sspec1=SLA3R|step1=E1|part1=LE80537LG0254M|sspec2=SLAET|step2=G0}}
 
−
{{cpulist|core|merom|model=Core 2 Duo SP7500
 
−
                                              |l2=4|fsb=800|mult=8|vmin=1.0|vmax=1.25|tdp=20|sock=µFC-BGA 956|price=OEM
 
−
  |sspec1=SLAT2|step1=|part1=SY80537GG0254M|sspec2=SLAEV|step2=}}
 
−
{{cpulist|core|merom|model=Core 2 Duo LV L7700 |l2=4|fsb=800|mult=9|vmin=0.9|vmax=1.1|tdp=17|sock=FCBGA6|date=September 2, 2007|price=$316
 
−
  |sspec1=SLAES|step1=G0|part1=LE80537LG0334M}}
 
−
{{cpulist|core|merom|model=Core 2 Duo SP7700|l2=4|fsb=800|mult=9|vmin=1.0|vmax=1.25|tdp=20|sock=µFC-BGA 956|price=OEM
 
−
  |sspec1=SLALQ|sspec2=SLALR|sspec3=SLASZ|step1=|part1=SY80537GG0334M|part2=SY80537GG0334ML}}
 
−
{{end}}
 
−
 
−
====="Merom-2M" (ultra-low-voltage, 65 nm)=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]]''
 
−
* [[Die (integrated circuit)|Die]] size: 111&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|L2, M0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|merom|model=Core 2 Duo U7500|sspec1=SLA2V|step1=L2|sspec2=SLAUT|step2=M0|freq=1066|l2=2|fsb=533|mult=8|vmin=0.750|vmax=0.925|tdp=10|sock=FCBGA6 (Socket&nbsp;M)|date=April 5, 2007|part1=LE80537UE0042M|price=$262|links=1}}
 
−
{{cpulist|core|merom|model=Core 2 Duo U7500|sspec1=SLV3X|step1=M0|freq=1066|l2=2|fsb=533|mult=8|vmin=0.750|vmax=0.925|tdp=10|sock=FCBGA6 (Socket&nbsp;P)|date=February 2008 |part1=LE80537UE0042M|price=$262}}
 
−
|-
 
−
|rowspan=2|Core 2 Duo U7600 || SLA2U (L2)<br>SLAUS (M0) ||rowspan=2| 1200 MHz ||rowspan=2| 2 MB ||rowspan=2| 533 MT/s ||rowspan=2| 9x ||rowspan=2| 0.750 - 0.925 V ||rowspan=2| 10 W || FCBGA6 (Socket&nbsp;M) || April 5, 2007 ||rowspan=2| LE80537UE0092M ||rowspan=2| $289
 
−
|-
 
−
|SLV3W (M0) || FCBGA6 (Socket&nbsp;P)||  April 2007
 
−
|-
 
−
|rowspan=2|Core 2 Duo U7700 || SLA6X (L2)<br>SLAUR (M0) ||rowspan=2|1333 MHz ||rowspan=2| 2 MB ||rowspan=2| 533 MT/s ||rowspan=2| 10x ||rowspan=2| 0.80 - 0.975 V ||rowspan=2| 10 W ||FCBGA6 (Socket&nbsp;M) || December 30, 2007 ||rowspan=2| LE80537UE0142M ||rowspan=2|$289
 
−
|-
 
−
|SLV3V (M0) || FCBGA6 (Socket&nbsp;P)||  February 2008
 
−
|}
 
−
 
−
====="[[Penryn (microprocessor)|Penryn]]" (Apple iMac specific, 45 nm)=====
 
−
* [[Die (integrated circuit)|Die]] size: 107&nbsp;mm²
 
−
* The 2008 20" iMac used the E8135 and E8335 CPUs at a lower than specified clock frequency, explaining why the same model is used at different frequencies. This list shows the frequencies used by Apple.
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel Core (microarchitecture)#Steppings using 45nm process|C0, E0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8135|fsb=1066|l2=6|mult=9|tdp=44|sock=[[Socket P]]|date=April 2008|
 
−
  sspec1=SLAQA|step1=C0|part1=FF80576E8135|part2=FF80576GH0676M|links=1}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8135|fsb=1066|l2=6|mult=10|tdp=44|sock=Socket P|date=March 2009|
 
−
  sspec1=SLG8W|step1=E0|part1=AW80576GH0676M|part2=AW80576E8135}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8135|fsb=1066|l2=6|mult=10|tdp=35|sock=Socket P|date=March 2009|
 
−
  sspec1=SLGED|step1=E0|part1=AW80576GH0676M}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8235|fsb=1066|l2=6|mult=10.5|tdp=44|sock=Socket P|date=April 2008|
 
−
  sspec1=SLAQB|step1=C0|part1=FF80576GH0726M}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8335|fsb=1066|l2=6|mult=10|tdp=44|sock=Socket P|date=April 2008|
 
−
  sspec1=SLAQC|step1=C0|part1=FF80576GH0776M}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8335|fsb=1066|l2=6|mult=11|tdp=35|sock=Socket P|date=March 2009|
 
−
  sspec1=SLGEB|step1=E0|part1=AW80576GH0776M}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8435|fsb=1066|l2=6|mult=11.5|tdp=55|sock=Socket P|date=April 2008|
 
−
  sspec1=SLAQD|step1=C0|part1=FF80576GH0836M}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo E8435|fsb=1066|l2=6|mult=11.5|tdp=44|sock=Socket P|date=March 2009|
 
−
  sspec1=SLGEA|step1=E0|part1=AW80576GH0836M}}
 
−
|}
 
−
 
−
====="Penryn", "Penryn-3M" (standard-voltage, 45 nm) {{Anchors|"Penryn-2M" (standard-voltage, 45 nm)|"Penryn-3M" (standard-voltage, 45 nm)|"Penryn" (standard-voltage, 45 nm)|Penryn-2M really does not exist)}}=====
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation),  iAMT2 (Intel Active Management), IDA (Intel Dynamic Acceleration)''
 
−
* T6670, all T8xxx and T9xxx models support [[Intel VT]]
 
−
* All T9xxx models support [[Trusted Execution Technology|TXT]]
 
−
* Note that the models T8100, T8300, T9300, T9500 are Penryn processors designed for Santa Rosa Refresh platforms with maximum FSB of 800 MHz, whereas the rest of the Penryn processors are designed for Montevina platforms that can go up to maximum FSB of 1066 MHz.
 
−
* Penryn processors support Dynamic Front Side Bus Throttling between 400MT/s and 800MT/s.
 
−
* [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² (Penryn), 82&nbsp;mm² (Penryn-3M)
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0, E0]] (Penryn) [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|M0, R0]] (Penryn-3M)
 
−
{{cpulist|core|head}}
 
−
| Core 2 Duo T6400 || SLGJ4 (R0)|| 2000 MHz ||rowspan="5"|2 MB ||rowspan="11"|800 [[Megatransfer|MT/s]] || 10x || rowspan="5"|1.00 - 1.25 V || 35 W || [[Socket P]] || rowspan="2"|January 6, 2009 || AW80577GG0412MA || OEM
 
−
|-
 
−
| Core 2 Duo T6500 || SLGF4 (R0) || 2100 MHz || 10.5x || 35 W || Socket P || AW80577GG0452ML<br>AW80577GG0452MA || OEM
 
−
|-
 
−
| Core 2 Duo T6570 || SLGLL (R0) || 2100 MHz || 10.5x || 35 W || Socket P || Q3, 2009 || AW80577GG0452MH  || OEM
 
−
|-
 
−
| Core 2 Duo T6600 || SLGJ9 (R0)<br>SLGF5 (R0)|| 2200 MHz || 11x || 35 W || Socket P || January 6, 2009 || AW80577GG0492MA<br>AW80577GG0492ML|| OEM
 
−
|-
 
−
| Core 2 Duo T6670 || SLGLK (R0) || 2200 MHz || 11x || 35 W || Socket P || Q3, 2009 ||AW80577GG0492MH  || OEM
 
−
|-
 
−
|rowspan=2| Core 2 Duo T8100 || SLAP9 (M0)<br>SLAVJ (M0)<br>SLAYP (M0)<br>SLAYZ (C0)<br>SLAUU (C0) ||rowspan=2| 2100 MHz ||rowspan=2| 3 [[Megabyte|MB]] ||rowspan=2| 10.5x ||rowspan=2| 1.00 - 1.250 V ||rowspan=2| 35 W || Socket P ||rowspan=2| January 6, 2008 || FF80577GG0453M&nbsp;(M0)<br>FF80576GG0453M&nbsp;(C0)<br>BX80577T8100 ||rowspan=2| $209
 
−
|-
 
−
|SLAPS (M0)<br>SLAXG (M0)<br>SLAPT (C0)<br>SLAZD (C0) || FCBGA6 || EC80577GG0453M&nbsp;(M0)<br>EC80576GG0453M&nbsp;(C0)
 
−
|-
 
−
|rowspan=2|Core 2 Duo T8300 || SLAPA (M0)<br>SLAYQ (M0) ||rowspan=2| 2400 MHz ||rowspan=2| 3 MB ||rowspan=2| 12x ||rowspan=2| 1.00 - 1.250 V ||rowspan=2| 35 W || Socket P ||rowspan=2| January 6, 2008 || FF80577GG0563M ||rowspan=2| $241
 
−
|-
 
−
|SLAPR (M0)<br>SLAPU (C0)<br>SLAZC (C0)|| FCBGA6 || EC80577GG0563M&nbsp;(M0)<br>EC80576GG0563M&nbsp;(C0)
 
−
|-
 
−
|rowspan=2| Core 2 Duo T9300 || SLAQG (C0)<br>SLAYY (C0) ||rowspan=2| 2500 MHz ||rowspan=2| 6 [[Megabyte|MB]] ||rowspan=2| 12.5x || 1.062 - 1.150 V ||rowspan=2| 35 W|| Socket P ||rowspan=2| January 6, 2008 || FF80576GG0606M ||rowspan=2| $316
 
−
|-
 
−
|SLAPV (C0)<br>SLAZB (C0)|| 1.00 - 1.250 V || FCBGA6 || EC80576GG0606M
 
−
|-
 
−
|rowspan=2| Core 2 Duo T9400 || SLB46 (C0)<br>SLB4D (C0)<br>SLGE5 (E0)|| rowspan=2 | 2533 MHz || rowspan=2 | 6 MB || rowspan=2| 1066 MT/s || rowspan=2| 9.5x || rowspan=2| 1.050 - 1.162V || rowspan=2| 35 W || Socket P || rowspan=2| July 14, 2008 || AW80576GH0616M || rowspan=2| $316
 
−
|-
 
−
|  SL3BX (C0)<br> SLGEK (E0) || FCBGA6 || AV80576GH0616M
 
−
|-
 
−
|rowspan=2| Core 2 Duo T9500 || SLAQH (C0)<br>SLAYX (C0)||rowspan=2| 2600 MHz ||rowspan=2| 6 MB ||rowspan=2| 800 MT/s ||rowspan=2| 13x || 1.062 - 1.150 V||rowspan=2| 35 W || Socket P ||rowspan=2| January 6, 2008 || FF80576GG0646M ||rowspan=2| $530
 
−
|-
 
−
| SLAPW (C0)<br>SLAZA (C0)<br>SLB49 (C0)<br>SLB4A (C0)<br>SLB4B (C0)|| 1.00 - 1.250 V|| FCBGA6 || EC80576GG0646M
 
−
|-
 
−
|Core 2 Duo T9550  || SLGE4 (E0)<br>SLGEL (E0)|| 2667 MHz || 6 MB || 1066 MT/s || 10x || 1.050 - 1.212V || 35 W || Socket P<br>FCBGA6 || December 28, 2008 || AW80576GH0676MG<br>AV80576GH0676MG || $316
 
−
|-
 
−
|rowspan=2| Core 2 Duo T9600 || SLB47 (C0)<br>SLG8N (C0)<br>SLG9F (E0)|| rowspan=2 | 2800 MHz || rowspan=2| 6 MB || rowspan=2| 1066 MT/s || rowspan=2| 10.5x || rowspan=2| 1.050 - 1.162V || rowspan=2| 35 W || Socket P || rowspan=2| July 14, 2008 || AW80576GH0726M || rowspan=2|$530
 
−
|-
 
−
| SLB43 (C0)<br> SLGEM (E0)|| FCBGA6|| AV80576GH0726M
 
−
|-
 
−
|Core 2 Duo T9800 || SLGES (E0)<br>SLGEP (E0) || 2933 MHz || 6 MB || 1066 MT/s || 11x || 1.050 - 1.212V || 35 W || Socket P<br>FCBGA6 || December 28, 2008 || AW80576GH0776MG<br>AV80576GH0776MG || $530
 
−
|-
 
−
| rowspan=2|Core 2 Duo T9900 || SLGEE (E0) || rowspan=2|3066 MHz || rowspan=2|6 MB || rowspan=2|1066 MT/s || rowspan=2|11.5x || rowspan=2|1.050V-1.2125V || rowspan=2|35 W || Socket P || rowspan=2|April 28, 2009 || AW80576GH0836MG || rowspan=2|$530
 
−
|-
 
−
| SLGKH (E0)|| FCBGA6|| AV80576GH0836MG
 
−
{{end}}
 
−
 
−
===== "Penryn", [[Penryn (microprocessor)#Penryn-3M|"Penryn-3M"]] (medium-voltage, 45 nm) {{anchors|"Penryn" (medium-voltage, 45 nm)|"Penryn-3M" (medium-voltage, 45 nm)}}=====
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]] (except the non-Mac P7350, P7450), [[Trusted Execution Technology|TXT]], IDA (Intel Dynamic Acceleration)''
 
−
* Select [[Apple Inc.|Apple]] subsets of P7000 series processors support Intel VT.
 
−
* Penryn and Penryn-3M processors support Dynamic Front Side Bus Throttling between 533MT/s and 1066MT/s.
 
−
* [[Die (integrated circuit)|Die]] size: 107&nbsp;mm² (Penryn), 82&nbsp;mm² (Penryn-3M)
 
−
* Package size: 35&nbsp;mm × 35&nbsp;mm
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0, E0]] (Penryn) [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|M0, R0]] (Penryn-3M)
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penryn|model=Core 2 Duo P7350|sspec1=SLB44|step1=C0|sspec2=SLB53|step2=M0|freq=2000|l2=3|fsb=1066|mult=7.5|vmin=1.00|vmax=1.250|tdp=25|date=Mid 2008 |part1=AW80576GH0413M|part2=AW80577SH0413M|price=OEM|links=1}}
 
−
|-
 
−
| rowspan=2| Core 2 Duo P7370 || rowspan=2| SLG8X (R0) || rowspan=2| 2000 MHz || rowspan=2| 3 MB || rowspan=2|  1066 MT/s || rowspan=2| 7.5x || rowspan=2|  1.00V - 1.250V || rowspan=2| 25 W || rowspan=2| Socket P || rowspan=2| January 2009 ||  AW80577SH0413M || rowspan=2| OEM
 
−
|-
 
−
| AW80577SH0413ML
 
−
|-
 
−
|Core 2 Duo P7450 || SLB45 (M0)<br>SLGF7 (R0)<br>SLB54 (C0) || 2133 MHz || 3 MB || 1066 MT/s || 8x || 1.00V - 1.250V || 25 W || Socket P || January 2009 || AW80577SH0463M<br>AW80576GH0463M (C0)|| OEM
 
−
|-
 
−
|Core 2 Duo P7550 || SLGVT<br>SLGF8 (R0) || 2266 MHz || 3 MB || 1066 MT/s || 8.5x || 1.00V - 1.250V || 25 W || Socket P || June 2009 || AW80577SH0513MA || OEM
 
−
|-
 
−
|Core 2 Duo P7570 || SLGLW (R0)|| 2266 MHz || 3 MB || 1066 MT/s || 8.5x || ?? || 25 W|| Socket P || Q3 2009 || AW80577SH0513ML || OEM
 
−
|-
 
−
| rowspan=2| Core 2 Duo P8400 || SLB3R (M0)<br>SLB3Q (M0)<br>SLB3R (M0)<br>SLB52 (M0)<br>SLG8Z (M0)<br>SLGCC (R0)<br>SLGCQ (R0)<br>SLGCF (R0)<br>SLGCL (R0)<br>SLCGC (R0)|| rowspan=2| 2266 MHz || rowspan=2 | 3 MB || rowspan=2 | 1066 MT/s || rowspan=2 | 8.5x || rowspan=2 | 1.00V - 1.250V || rowspan=2 | 25&nbsp;W || Socket P || rowspan=2 | June 13, 2008 || AW80577SH0513M<br>AW80577SH0513MN<br>BX80577P8400 || rowspan=2| $209
 
−
|-
 
−
| SL3BU (C0)<br>SLB4M (M0)<br>SLGE2 (R0) || FCBGA6 || AV80576SH0513M&nbsp;(C0)<br>AV80577SH0513M
 
−
|-
 
−
| rowspan=2| Core 2 Duo P8600 || SLB3S (M0)<br>SLGA4 (M0)<br>SLGFD (R0)<br>SLGDZ (R0)|| rowspan=2| 2400 MHz || rowspan=2 | 3&nbsp;MB || rowspan=2 | 1066 MT/s || rowspan=2 | 9x || rowspan=2 | 1.00V - 1.250V || rowspan=2 | 25 W || Socket&nbsp;P || rowspan=2 | June 13, 2008 || AW80577SH0563M<br>BX80577P8600  || rowspan=2| $241
 
−
|-
 
−
| SLB4N (M0)<br>SL3BV (C0)<br>SLGDZ (R0)|| FCBGA6 || AV80576SH0563M&nbsp;(C0)<br>AV80577SH0563M
 
−
|-
 
−
|Core 2 Duo P8700  || SLGFE (R0)<br>SLGFG (R0)|| 2533 MHz || 3 MB || 1066 MT/s || 9.5x || 1.00V - 1.250V || 25 W || Socket P<br>FCBGA6 || December 28, 2008 || AW80577SH0613MG<br>AV80577SH0613MG || $241
 
−
|-
 
−
|Core 2 Duo P8800 || SLGLR (R0)<br>SLGLA (E0)|| 2667 MHz || 3 MB || 1066 MT/s || 10x || 1.00V - 1.250V || 25 W <br>35 W|| Socket P<br>FCBGA6 || Q2, 2009 || AW80577SH0673MG<br>AV80577SH0673MG<br>BX80577P8800|| $241
 
−
|-
 
−
| Core 2 Duo P9500 || SLB4E (C0)<br>SLGE8 (E0)<br>SL3BW (C0) || 2533 MHz || 6 [[Megabyte|MB]] || 1066 [[Megatransfer|MT/s]] || 9.5x || 1.050V - 1.162V || 25 W || Socket P<br>FCBGA6 || July 14, 2008 || AW80576SH0616M<br>AV80576SH0616M || $348
 
−
|-
 
−
| Core 2 Duo P9600 || SLGE6 (E0)|| 2667 MHz || 6 MB || 1066 MT/s || 10x || 1.050V - 1.212V || 25 W || Socket P  || December 28, 2008 || AW80576SH0676MG || $348
 
−
|-
 
−
| Core 2 Duo P9700 || SLGQS (E0) || 2800 MHz || 6 MB || 1066 MT/s || 10.5x || 1.012V-1.175V || 28 W || Socket P || June 2009 || AW80576SH0726MG || $348
 
−
|}
 
−
 
−
====="Penryn" (medium-voltage, 45 nm, Small Form Factor)=====
 
−
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]], IDA (Intel Dynamic Acceleration)''
 
−
* [[Die (integrated circuit)|Die]] size: 107&nbsp;mm²
 
−
* Package size: 22&nbsp;mm × 22&nbsp;mm
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0]], [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|E0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SP9300|sspec1=SLB63|step1=C0|sspec2=SLGAF|step2=E0|freq=2266|l2=6|fsb=1066|mult=8.5|vmin=0.900|vmax=1.250|tdp=25|date=July 2008|part1=AV80576SH0516M|price=$284|links=1}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SP9400|sspec1=SLB64|step1=C0|sspec2=SLGHG|step2=C0|freq=2400|l2=6|fsb=1066|mult=9|vmin=0.900|vmax=1.250|tdp=25|date=July 2008|part1=AV80576SH0566M|price=$284|sspec3=SLGAA|step3=E0}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SP9600|sspec1=?????|step1=C0|sspec2=SLGER|step2=E0|freq=2533|l2=6|fsb=1066|mult=9.5|vmin=0.900|vmax=1.250|tdp=25|date=Q1 2009|part1=AV80576SH0516M|part2=AV80576SH0616M|price=$316}}
 
−
{{end}}
 
−
 
−
====="Penryn" (low-voltage, 45 nm, Small Form Factor)=====
 
−
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]], IDA (Intel Dynamic Acceleration)''
 
−
* [[Die (integrated circuit)|Die]] size: 107&nbsp;mm²
 
−
* Package size: 22&nbsp;mm × 22&nbsp;mm
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0]], [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|E0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SL9300|sspec1=SLB65|step1=C0|sspec2=SLGHC|step2=C0|sspec3=SLGAG|step3=E0|freq=1600|l2=6|fsb=1066|mult=6|vmin=1.050|vmax=1.150|tdp=17|date=September 2008|part1=AV80576LH0256M|price=$284|links=1}}
 
−
|-
 
−
| Core 2 Duo SL9380 || SLGA2 (C0)<br>SLGAD (E0) || 1800 MHz || 6 MB || 800 MT/s || 9x || 1.050 - 1.150 V || 17 W || FCBGA6 || September 2008 || AV80576LG0336M ||  $316
 
−
|-
 
−
| Core 2 Duo SL9400 || SLB66 (C0)<br>SLGHD (C0)<br>SLGAB (E0) || 1866 MHz || 6 MB || 1066 MT/s || 7x || 1.050 - 1.150 V || 17 W || FCBGA6 || September 2008 || AV80576LH0366M ||  $316
 
−
|-
 
−
| Core 2 Duo SL9600 || SLGEQ (E0) || 2133 MHz ||6 MB || 1066 MT/s || 8x || 1.050 - 1.150V || 17 W || FCBGA6 || Q1'09 || AV80576LH0466M  ||  $316
 
−
{{end}}
 
−
 
−
====="Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)=====
 
−
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]], IDA (Intel Dynamic Acceleration)''
 
−
* [[Die (integrated circuit)|Die]] size: 82&nbsp;mm²
 
−
* Package size: 22&nbsp;mm × 22&nbsp;mm
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|M0]], [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|R0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SU7300|l2=3|mult=6.5|date=September 2009|fsb=800|price=$289|links=1
 
−
  |sspec1=SLGS6|step1=R0|sspec2=SLGYV|step2=R0|part1=AV80577UG0133M|part2=AV80577UG0133ML}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SU7800|l2=3|mult=7  |date=September 2009|fsb=800|price=$289
 
−
  |part1=AV80577UG0173M|sspec1=SLGS5|step1=R0}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SU9300|l2=3|mult=6  |date=September 2008|fsb=800|price=$262|vmin=1.050|vmax=1.150
 
−
  |part1=AV80577UG0093M|sspec1=SLB5Q|step1=M0|sspec2=SLGAL|step2=R0}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SU9400|l2=3|mult=7  |date=September 2008|fsb=800|price=$289|vmin=1.050|vmax=1.150
 
−
  |part1=AV80577UG0173M|sspec1=SLB5V|step1=M0|sspec2=SLGHN|step2=M0|sspec3=SLGAK|step3=R0}}
 
−
{{cpulist|core|penrynulv|model=Core 2 Duo SU9600|l2=3|mult=8  |date=Q1'09        |fsb=800|price=$289|vmin=1.050|vmax=1.150
 
−
  |part1=AV80577UG0253M|sspec1=SLGEX|step1=R0|sspec2=SLGFN|step2=R0}}
 
−
{{end}}
 
−
 
−
====Core 2 Extreme====
 
−
===== [[Merom (microprocessor)#Merom XE|"Merom XE"]] (standard-voltage, 65 nm)=====
 
−
''These models feature an [[CPU locking|unlocked]] [[clock multiplier]]''
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]], Intel Dynamic Front Side Bus Frequency Switching''
 
−
* Merom XE processors support Dynamic Front Side Bus Throttling between 400 MHz and 800 MHz.
 
−
* [[Die (integrated circuit)|Die]] size: 143&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_65nm_process|E1, G0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|merom|model=Core 2 Extreme X7800|sspec1=SLA6Z|step1=E1|freq=2600|l2=4|fsb=800|mult=13|vmin=1.0375|vmax=1.3|tdp=44|date=July 16, 2007|sock=[[Socket P]]|part1=LF80537GG0644M|price=$851|links=1}}
 
−
{{cpulist|core|merom|model=Core 2 Extreme X7900|sspec1=SLA33|step1=E1|sspec4=SLAF4|step4=G0|freq=2800|l2=4|fsb=800|mult=14|vmin=1.0375|vmax=1.3|tdp=44|sock=Socket P|date=August 22, 2007|part1=LF80537GG0724M|price=$851}}
 
−
{{end}}
 
−
 
−
===== [[Penryn (microprocessor)#Penryn XE|"Penryn XE"]] (standard-voltage, 45 nm)=====
 
−
*These models feature an [[CPU locking|unlocked]] [[clock multiplier]]''
 
−
*All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]],  [[Trusted Execution Technology|TXT]]''
 
−
* Penryn XE processors support Dynamic Front Side Bus Throttling between 400 MHz to 800 MHz and 533 MHz to 1066 MHz.
 
−
* [[Die (integrated circuit)|Die]] size: 107&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|C0, E0]]
 
−
{| class="wikitable"
 
−
!Model Number !! sSpec Number !! Clock Speed !! L2 Cache !! FSB Speed !! Clock Multiplier !! Voltage Range !! TDP !! Socket !! Release Date !! Part Number(s) !! Release Price (USD)
 
−
|-
 
−
{{cpulist|core|penryn|model=Core 2 Extreme X9000|sspec1=SLAQJ|step1=C0|sspec2=SLAZ3|step2=C0|l2=6|fsb=800|mult=14|vmin=1.062|vmax=1.150|tdp=44|date=January 7, 2008|part1=FF80576ZG0726M|price=$851|links=1}}
 
−
{{cpulist|core|penryn|model=Core 2 Extreme X9100|sspec1=SLB48|step1=C0|sspec2=SLG8M|step2=C0|sspec3=SLGE7|step3=E0|l2=6|fsb=1066|mult=11.5|vmin=1.062|vmax=1.150|tdp=44|date=July 15, 2008|part1=AW80576GH0836M|price=$851}}
 
−
|}
 
−
 
−
===Quad-Core Notebook processors===
 
−
====Core 2 Quad====
 
−
===== [[Penryn (microprocessor)#Penryn-QC|"Penryn QC"]] (standard-voltage, 45 nm)=====
 
−
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]]''
 
−
* Socket P processors are capable of throttling the FSB anywhere between 533-1066 MHz as necessary. Note that reports are stating this chip is a socket P' [sic] and as such may not be pin compatible with standard Socket P motherboards. Announcements closer to the time may clarify this situation.
 
−
* Package size: 35&nbsp;mm × 35&nbsp;mm
 
−
* [[Die (integrated circuit)|Die]] size: 2 × 107&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|E0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penrynqc|model=Core 2 Quad Q9000|sspec1=SLGEJ|step1=E0|freq=2.00|l2=2 × 3 [[Mebibyte|MiB]]|fsb=1066|mult=7.5|vmin=1.050|vmax=1.175|tdp=45|sock=P|date=December 28, 2008|part1=AW80581GH0416M|part2=BX80581Q9000|price=$348|links=1}} 
 
−
{{cpulist|core|penrynqc|model=Core 2 Quad Q9100|sspec1=SLB5G|step1=E0|freq=2.26|l2=2 × 6 MiB|fsb=1066|mult=8.5|vmin=1.050|vmax=1.175|tdp=45|sock=P|date=August 19, 2008|part1=AW80581GH051003|price=$851}} 
 
−
{{end}}
 
−
 
−
====Core 2 Extreme====
 
−
====="Penryn QC XE" (standard-voltage, 45 nm)=====
 
−
 
−
* These models feature an [[CPU locking|unlocked]] [[clock multiplier]]'' usually manipulated through the systems BIOS however some manufacturers (such as [[HP]]) do not have this feature enabled on their laptops that use this processor.
 
−
* All models support: ''[[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4|SSE4.1]], Enhanced Intel [[SpeedStep]] Technology (EIST), [[Intel 64]], XD bit (an [[NX bit]] implementation), iAMT2 (Intel Active Management), [[Intel VT]], [[Trusted Execution Technology|TXT]]''
 
−
* Socket P processors are capable of throttling the FSB anywhere between 533-1066 MHz as necessary. Note that reports are stating this chip is a socket P' [sic] and as such may not be pin compatible with standard Socket P motherboards. Announcements closer to the time may clarify this situation.
 
−
* Package size: 35&nbsp;mm × 35&nbsp;mm
 
−
* [[Die (integrated circuit)|Die]] size: 2 × 107&nbsp;mm²
 
−
* [[Stepping (version numbers)|Steppings]]: [[Intel_Core_(microarchitecture)#Steppings_using_45nm_process|E0]]
 
−
{{cpulist|core|head}}
 
−
{{cpulist|core|penrynqc|model=Core 2 Extreme QX9300|sspec1=SLB5J|step1=E0|freq=2533|l2=2 × 6 [[Mebibyte|MiB]]||fsb=1066|mult=9.5|vmin=1.050|vmax=1.175|tdp=45|sock=P|date=August 19, 2008|part1=AW80581ZH061003|price=$1038|links=1}}
 
−
<!--
 
−
{{cpulist|core|penrynqc|model=Core 2 Extreme QX9400|sspec1=SLB5K|step1=E0|freq=2667|l2=2 × 6 MiB||fsb=1066|mult=10|vmin=1.050|vmax=1.175|tdp=45|sock=P|date=|part1=AW80581ZH067003|price=}} -->
 
−
{{end}}
 
−
 
−
==See also==
 
−
*[[Intel Core 2]]
 
−
*[[Comparison of Intel processors]]
 
−
*[[List of Intel codenames]]
 
−
*[[List of future Intel microprocessors]]
 
−
*[[List of Intel Pentium Dual-Core microprocessors]]
 
−
*[[List of Intel Core i7 microprocessors]]
 
−
*[[Engineering sample (CPU)]]
 
−
 
−
==References==
 
−
{{reflist}}
 
−
 
−
{{refbegin}}
 
−
*[http://www.reghardware.co.uk/2006/05/23/ati_confirms_intel_allendale/ ATI provides pointer to Intel's 'Allendale'], 23 May 2006
 
−
*[http://www.theinquirer.net/default.aspx?article=32026 Rumoured prices and specifications for Intel Core 2], 30 May 2006
 
−
*[http://www.tgdaily.com/2006/07/24/intel_to_launch_core_2_duo TGDaily indicates leaked release dates], 24 July 2006
 
−
*[http://digitimes.com/mobos/a20060717PB213.html Intel to unveil five Merom CPUs in July, paper says] as re-reported by DigiTimes, 17 July 2006
 
−
*[http://www.intel.com/pressroom/archive/releases/20060727comp.htm Intel Unveils World's Best Processor], 27 July 2006
 
−
*[http://www.intel.com/pressroom/archive/releases/20070716corp_a.htm?iid=pr1_releasepri_20070716ar Intel Takes Popular Laptops to 'Extreme' with First-Ever Extreme Edition Mobile Processor; Adds New Desktop Chip], 16 July 2007
 
−
*[http://xtreview.com/addcomment-id-2933-view-Core-2-duo-1333-mhz-stepping.html CORE 2 DUO 1333 MHZ STEPPING], 18 July 2007
 
−
{{refend}}
 
−
 
−
==External links==
 
−
*[http://ark.intel.com/sspecqdf.aspx SSPEC/QDF Reference] (Intel)
 
−
*[http://www.intel.com/products/processor_number/chart/core2xe.htm Intel Core 2 Extreme processor numbers]
 
−
*[http://www.intel.com/products/processor_number/chart/core2quad.htm Intel Core 2 Quad processor numbers]
 
−
*[http://www.intel.com/products/processor_number/chart/core2duo.htm Intel Core 2 Duo processor numbers]
 
−
*[http://www.intel.com/products/processor_number/chart/core2solo.htm Intel Core 2 Solo processor numbers]
 
−
*[http://www.intel.com/products/processor/core2duo/index.htm Intel Core 2 Duo product page]
 
−
*[http://www.intel.com/products/processor/core2XE/index.htm Intel Core 2 Extreme product page]
 
−
*[http://www.intel.com/pressroom/archive/releases/20060727comp.htm Intel press release about the announcement of desktop and mobile Core 2 processors]
 
−
*[http://media.corporate-ir.net/media_files/irol/10/101302/Jan_20_08_1ku_Price.pdf Intel Processor Pricing]
 
−
*[http://www.reghardware.co.uk/2006/05/08/intel_core_2_brand/ Naming and Availability]
 
−
*[http://www.xbitlabs.com/news/cpu/display/20060525154847.html Model numbers]
 
−
*[http://www.intel.com/design/intarch/core2duo/tech_docs.htm Intel Core 2 Duo Processors Technical Documents]
 
−
*[http://www.intc.com/priceList.cfm Intel Corporation - Processor Price List]
 

Latest revision as of 13:04, 10 February 2010

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